In a liquid crystal display, an operational amplifier has been in use as an amplifier in driving a load on a data line. For example, an operational amplifier shown in FIG. 13 comprises a differential amplifier 901 and an output stage amplifier circuit 903. Of these, the differential amplifier 901 includes a differential pair, composed of NMOS transistors M3 and M4, having sources connected in common, and an active load circuit, which is a current mirror. This current mirror is composed of a PMOS transistor M1, having a source connected to a power supply VDD (high side power supply or positive power supply) and having its gate connected to its drain, and a PMOS transistor M2, having a source connected to the power supply VDD and having a gate connected in common to the gate of the PMOS transistor M1. The differential amplifier 901 also includes an NMOS transistor M9 having a source connected to a power supply VSS (low side power supply or negative power supply) and having a drain connected to common sources of NMOS transistors M3 and M4. The NMOS transistor M9 has a gate supplied with a constant voltage and operates as a constant current source. In the example shown in FIG. 13, the output stage amplifier circuit 903 is designed and constructed as a common source active load amplifier circuit, and is composed of a PMOS transistor M7 and an NMOS transistor M10. The PMOS transistor M7 has a source connected to the power supply VDD, while having a gate connected to an output point PA of the differential amplifier circuit and having a drain connected to an output terminal VOUT. The NMOS transistor M10 has a source connected to the power supply VSS, while having a drain connected to the drain of the PMOS transistor M7 and having a gate supplied with a bias voltage VBIAS to constitute a constant current source. The NMOS transistor M4 has a gate connected to an input terminal VIN. The output terminal VOUT is connected in a feedback fashion to the gate of the NMOS transistor M3.
The voltage at the output terminal VOUT (voltage at an output point PB) is determined by a balanced point between the drain current of the PMOS transistor M7 of the output stage amplifier circuit 903, determined in turn by the voltage at the input terminal VIN, and the drain current of the NMOS transistor M10 of the constant current source.
However, an operational amplifier suffers from an output offset voltage produced due to variations in characteristics of mainly the active elements such as transistors. These variations in characteristics are due in turn to fluctuations in an oxide film of a MOS transistor, in impurity concentrations or in device size W/L, where W is the channel width and L is a channel length. These fluctuations are derived from the fabrication process and are unavoidable despite endeavors in designing, such as adjustments of element sizes.
In particular, the variations in characteristics of a transistor of a differential circuit section appear pronouncedly as output offset. Ideally, the NMOS transistors M3 and M4 are of the same characteristics, while the PMOS transistors M1 and M2 are also of the same characteristics. However, in actuality, the transistor characteristics are not wholly of the same characteristics, due to constraints in the fabrication process, as described above.
In general, the offset voltage ascribable to fluctuations in characteristics of the transistors of the differential circuit section is proportionate to 1/√{square root over ( )}S, where S denotes the transistor gate area of the transistor. Thus, for reducing the offset voltage, the gate needs to be of a broader area. This increases the chip area, such that there is imposed a limitation in case the offset voltage itself is high. For coping with this problem, a circuit (offset cancellation amplifier) is used for correcting the output offset through use of a capacitance element.
FIG. 14 shows a configuration of an offset cancellation amplifier, which has so far been used, and FIG. 5 is a timing diagram for illustrating its control method. A circuit for offset cancellation 811 includes an offset detection capacitor Coff and switches 801 to 803. The capacitor Coff has one end connected via a switch (S2) 802 to an input terminal VIN, while having the other end connected to an inverting input terminal (−) of an operational amplifier 810. A switch (S1) 801 is connected between the inverting input terminal (−) of the operational amplifier 810 and an output terminal VOUT, while a switch (S3) 803 is connected between a connection point of the capacitor Coff to the switch S2 and the output terminal VOUT.
A voltage Vin, received by the input terminal VIN of the operational amplifier 810, is supplied to a non-inverting input terminal (+) of the operational amplifier 810. The output terminal VOUT of the operational amplifier 810 is output to outside to drive a load, not shown, connected to outside.
The operation of the offset cancellation amplifier, shown in FIG. 14, will now be described with reference to the timing diagram of FIG. 15. Meanwhile, in FIG. 15, symbols S1, S2 and S3 correspond to switches (S1) 801, (S2) 802 and (S3) 803 of FIG. 14, respectively. Each data output period is composed of an offset detection period T01 and an offset correction output period T02.
During the offset detection period T01, the switches S1 and S2 are in an on state, and the switch S3 is turned off. This sets one end of the offset detection capacitor Coff to the input terminal VIN, with the potential of the one end of the capacitor being set to the input voltage VIN. Since the switch S1 is on, the potential of the other end of the capacitor Coff is set at the output voltage Vout.
Hence, the voltage applied across the terminals of the capacitor Coff isVout−Vin=(Vin+Voff)−Vin=Voffso that electric charge equivalent to the offset voltage Voff is accumulated in the capacitor Coff (offset detection period).
During the offset correction output period T02, the switches S1 and S2 are in an off state, and thereafter the switch S3 is in an on state. Since the switches S1 and S2 are in an off state, the offset voltage Voff, the offset voltage Voff keeps on to be retained in the capacitor Coff. By setting the switch S3 on, a voltage corresponding to the output voltage Vout during the period T01, as a reference voltage, less the offset voltage Voff, is applied to the inverting input terminal (−) of the operational amplifier 810
As a result, the output voltage Vout isVout=(Vin+Voff)−Voff=Vinand hence the offset voltage is corrected to allow for outputting the voltage in high accuracy (offset correction output period).
However, the above-described conventional offset cancellation amplifier is plagued with the following problem.
That is, since the input terminal VIN is connected to one end of the capacitor Coff, the effective input capacitance of the amplifier is increased. The smaller the input capacitance of the amplifier, the smaller is power consumption. On the other hand, a certain moderate magnitude of the offset detection capacitor Coff is needed in order to maintain the voltage for a preset period of time and in order to minimize an offset error ascribable to electric charge generated when the switch is off.
In addition, in the case of the offset cancellation amplifier, shown in FIG. 14, the input terminal VIN and the output terminal VOUT are electrically connected to each other during the time period T01 via the capacitor Coff to constitute a positive feedback loop. Thus, in case an external power supply for supplying the voltage to the input terminal VIN is low in supply capacity, there are cases where the output voltage becomes unstable.
For the above reason, it is not desirable to connect a capacitance element to the input terminal VIN of the amplifier.
In the case of a TFT (Thin Film Transistor), manufactured by a low temperature polysilicon process, the threshold values of transistors making up the TFT circuit exhibit significant fluctuations. Hence, the offset cancellation amplifier of FIG. 14 is unable to correct the offset completely, with the result that output offset may be produced or the circuit operation may be disabled.
An offset cancellation amplifier, with which it is possible to solve the aforementioned problem of increased input capacitance or defects in the circuit operation, is disclosed in for example Patent Document 1 (JP Patent 2001-292401). FIGS. 16 and 17 hereof show the circuit configuration and a timing diagram for illustration of the control method, respectively. Referring to FIG. 16, the circuit includes NMOS transistors M5 and M6, having sources connected in common to form a differential pair, and NMOS transistors M3 and M4, having sources connected in common to form another differential pair. The circuit also includes an NMOS transistor M8 having a source connected to a power supply VSS, while having a drain connected to the common source of the differential pair (M5, M6) and having a gate supplied with a VBIA voltage to constitute a current source. The circuit also includes an NMOS transistor M9 having a source connected to the power supply VSS, while having a drain connected to the common source of the differential pair (M3, M4) and having a gate supplied with the VBIA voltage to constitute a current source. The circuit also includes a current mirror circuit, composed of PMOS transistors M1 and M2, and constitutes a common active load for the differential pairs (M3, M4) and (M5, M6). The PMOS transistor M1 has a source connected to the power supply VDD, and has a drain and a gate connected together, while the PMOS transistor M2 has a source connected to the power supply VDD and has a gate connected to the gate of the PMOS transistor M1. The circuit also includes a PMOS transistor M7, having a source connected to the power supply VDD, while having a gate connected to a connection point between the drains of the MOS transistors M2 and M4 and having a drain connected to the output terminal VOUT. The circuit also includes an NMOS transistor M10, having a source connected to the power supply VSS, while having a drain connected to the output terminal VOUT and having a gate supplied with the VBIAS voltage. The circuit also includes switches S1 and S2 between the input terminal VIN and the gate of the NMOS transistor M3 and between the output terminal VOUT and the gate of the NMOS transistor M3, and a switch S3 between the gate of the NMOS transistor M5 and the output terminal VOUT. The circuit further includes a capacitor C1 between the gate of the NMOS transistor M5 and the power supply VSS.
The operation of the offset cancellation amplifier, disclosed in Patent Document 1, will now be described with reference to the circuit configuration of FIG. 16 and to the timing diagram of FIG. 17. During an offset detection period T01 of one data output period TDATA, the switches S1 and S3 are in an on state, while the switch S2 is turned off. At this time, the differential pair (M3, M4) both receives the input voltage Vin, supplied to the input terminal VIN, so that the differential pair (M3, M4) operates as a current source for the current mirror circuit (M1, M2). Out of the transistors of the differential pair (M5, M6), the transistor M6 has a gate connected to the input terminal VIN, and the transistor M5 has a gate connected to the output terminal VOUT. In this case, the voltage Vout of the output terminal is stabilized, by a negative feedback operation, to a voltage inclusive of an offset voltage Voff, ascribable to fluctuations in characteristics of the transistors in the differential circuit, that is, (Vin+Voff). Since the capacitor C1 is connected to the gate of the transistor M5, the potential of Vout in the stabilized state is set in the capacitor.
During an offset correction output period T02 of one data output period, the switches S1 and S3 are in an off state, while the switch S2 is in an on state. At this time, the same voltage as that applied during the period T01 keeps on to be supplied to the differential pair (M5, M6). Since the input terminal remains connected to the gate of the transistor M4, and the output terminal VOUT is connected to the gate of the transistor M3, in a negative feedback fashion, the voltage Vout is stabilized at a potential which is the same as one during the time period T01. That is, the output voltage Vout becomes equal to the input voltage Vin, during the time period T02, thus correcting the offset.
The offset cancellation amplifier in the example of Patent Document 1 is desirable since a capacitance element for offset detection is not connected to the input terminal VIN of the amplifier, and hence the input capacitance is not increased due to addition of the circuit for offset cancellation, while the amplifier has high operational stability.
In addition, a modification of FIG. 16, shown in FIG. 18, is configured for suppressing the adverse effect of the ground noise or the power supply noise. A capacitor C2 is connected across the gate of an NMOS transistor M6, as one of the transistors of the differential pair, while a switch S6 is connected across the gate of transistor M6 and the input terminal VIN.
The operation of the circuit configuration of FIG. 18 will now be described with reference to the timing diagram of FIG. 19. During the offset detection period T01, the switches S1, S3 and S6 are in an on state, while the switch S2 is turned off. Hence, the input voltage Vin is supplied to the differential pair (M3, M4), and the differential pair (M3, M4) operates as a current source for the current mirror circuit (M1, M2). The transistors M5 and M6 forming the differential pair, is supplied with the output voltage Vout and the input voltage Vin, respectively. At this time, the input voltage Vin is accumulated in the capacitor C2, while a voltage composed of the input voltage and the offset voltage Vof added thereon (Vin+Vof) is accumulated in the capacitor C1.
Next, during the offset correction output period T02, the switches S1, S3 and S6 are in an off state, while the switch S2 is in an on state. At this time, the voltage (Vin+Vof), accumulated and retained in the capacitor C1, and the voltage Vin, accumulated and retained in the capacitor C2, are supplied to input pairs of the differential pair (M5, M6), respectively. The output voltage Vout and the input voltage Vin are supplied to input pairs of the differential pair (M3, M4), respectively. With the circuit of FIG. 18, as in the circuit of FIG. 16, it is possible to cancel the output offset and to output an amplified voltage which is approximately equal to the input voltage.
Here, the properties of the differential circuit of amplifying a differential signal and removing in-phase signals are exploited. Hence, the adverse effect of the power supply noise due to VSS may be removed. That is, with the configuration shown in FIG. 18, it is possible to output the voltage more accurately than with the configuration of FIG. 16.
The circuit configuration of FIG. 18 may be modified as illustrated in Patent Document 2 (JP Patent Kokai Publication No. JP-P2003-168936A). FIG. 20 shows the so modified configuration.
The configuration of FIG. 20 is modified from the circuit of FIG. 18 in supplying a reference voltage VREF to the gate of the NMOS transistor M6. The switches S1 to S3 are controlled in the same way as shown in the timing diagram of FIG. 19.
The configuration of FIG. 20 differs from that of FIG. 18 in supplying (Vref+Vof) and Vref to the input pair of the differential pair (M5, M6). That is, the reference voltage Vref at a reference voltage supply terminal VREF may be optionally set.
Meanwhile, this reference voltage Vref may be set as a median voltage at the output voltage range of the amplifier circuit for further decreasing the potential fluctuations of the output voltage Vout during the time period T01. As a result, the time T01 as the time for preparing for offset cancellation may be made shorter to provide for a longer time for the time period T0 in which to carry out correction outputting.
As the configuration for shortening the offset detection period, there is known a circuit configuration shown in Patent Document 3 (JP Patent Kokai Publication No. JP-P2005-117547A). FIGS. 21 and 22 depict the circuit configuration and a timing diagram for controlling the switches, respectively. The circuit configuration of FIG. 21 presets the output voltage Vout, which prevailed one horizontal period before, that is, one output period before, as a reference voltage Vref of the output configuration of FIG. 20, in the capacitor C2, to provide for a shorter offset detection time.
The principle of shortening the offset detection time will now be described with reference to the circuit diagram of FIG. 21 and to the timing diagram shown in FIG. 22.
The input voltage for the first horizontal period H1 and that for the second horizontal period H2 are labeled Vin1 and Vin2, respectively.
During a time T02 of the first horizontal period H1, the switch S2 is turned on, while the switches S1 and S3 are turned off. At this time, the switch S4 is off. Since the offset is canceled for the reason as stated later, the output voltage is such that Vout1=Vin1.
When the switch S4 is turned on during the time T03 provided within the time T02, the output terminal VOUT is connected to both the capacitor C2 and the gate of M6. At this time, Vout1, that is, Vin1, is accumulated in the capacitor C2. When the voltage at the capacitor C2 is stabilized sufficiently, S4 is turned off, so that Vout1 (=Vin1) is retained in the capacitor C2.
During the time T01 of the next horizontal period H2, the switches S1 and S3 are turned on, while the switch S2 is turned off. At this time, (Vin2, Vin2) are applied to the input pair of the differential pair (M3, M4), while (Vout1+Vof, Vout1) are applied to the inputs pair of the differential pair (M5, M6). Since the voltage at the output end Vout (voltage at PB) is necessarily stabilized at this time, that is, at the end of the horizontal period H1, it is sufficient to vary only the output potential by only a difference Vof from Vout1, at the start time point of the horizontal period H2, thus providing for a shorter offset detection time.
However, the circuit configuration of FIG. 21 suffers from the problem that the output voltage Vout is varied during time T03, thus worsening output correction accuracy. Such problem arises from differential voltages applied to the inputs of the differential pair (M5, M6) before and after start of the time T03 during the horizontal period H2, as will now be described.
That is, directly before the beginning of the time T03, (Vout1+Vof1, Vout2) are supplied to the input pair of the differential pair (M5, M6). (Vout2, Vin2) keep on to be applied to the inputs of the differential pair (M3, M4). The output terminal VOUT is connected at this time to both the non-inverting input terminal of the first differential pair (gate of M6) and the inverting input terminal of the second differential pair (gate of M5), so that positive feedback is partially applied.
During the horizontal period H2, only the voltage Vout2 at the output terminal may be varied. Hence, the voltage applied to the gate of the transistor M6 is Vout2, during the period T03, thus upsetting the drain current balance of the two differential pairs. As a result, the output potential Vout during the time T03 is increased or decreased, depending on the input states of the differential pairs, thus worsening output accuracy.
[Patent Document 1] JP Patent Kokai Publication No. JP-P2001-292041A
[Patent Document 2] JP Patent Kokai Publication No. JP-P2003-168936A
[Patent Document 3] JP Patent Kokai Publication JP-P2005-117547A
[Non-Patent Document 1] Design and Application of Analog CMOS Integrated Circuit, translated by Tadahiro Kuroda et al. pp 508-515, Maruzen, 2003